The present invention relates generally to integrated circuit transistors and in particular the present invention relates to methods of forming damascene transistor gates having a notched profile.
Integrated circuit manufacturers continually strive to scale down semiconductor devices in integrated circuit chips. Smaller scale semiconductor devices translate to increased speed and capacity while reducing power consumption. For example, in order to provide increased capacity in memory chips such as SRAM, it is highly desirable to shrink the size of each memory cell without significantly affecting performance. This may be accomplished by shrinking the size of each component of the memory cell, packing the components closer together, or both.
Integrated circuit transistors have source and drain regions and a gate electrode. The transistors are typically fabricated such that each have a doped polysilicon gate electrode. The source and drain regions are typically implanted into a substrate of silicon. A channel region is defined between the source and drain regions and beneath the gate electrode. A capacitance, known as overlap capacitance, may be created between the gate and the source/drain regions where the gate overlaps the source/drain regions. This capacitance affects how the transistor functions and is undesirable.
Additionally, for high performance devices, such as SRAM, it is desirable to form the shortest channel length transistors at a given lithography node. The channel length is the distance between the source and the drain. However, lithographic processes are limited, and fabrication processes are exploited to form transistors having channel lengths shorter than those possible with lithography alone. One such fabrication process is taught in U.S. Pat. No. 5,834,817 to Satoh et al. Satoh et al. utilizes a plasma etching method and layers having different etching speeds to form shaped gate electrodes. However, this method can present difficulties with control of notch height and depth over a wide process range. Therefore, a need exists for a method of forming notched gate electrodes that allows the notch height and depth to be independently adjusted while providing transistors with shorter channel length and reduced overlap capacitance.